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C8051F380/1/2/3/4/5/6/7/C
10. Power Management Modes
The C8051F380/1/2/3/4/5/6/7/C devices have three software programmable power management modes:
Idle, Stop, and Suspend. Idle mode and stop mode are part of the standard 8051 architecture, while sus-
pend mode is an enhanced power-saving mode implemented by the high-speed oscillator peripheral.
Idle mode halts the CPU while leaving the peripherals and clocks active. In stop mode, the CPU is halted,
all interrupts and timers (except the Missing Clock Detector) are inactive, and the internal oscillator is
stopped (analog peripherals remain in their selected states; the external oscillator is not affected). Sus-
pend mode is similar to stop mode in that the internal oscillator is halted, but the device can wake on activ-
ity with the USB transceiver. The CPU is not halted in suspend mode, so it can run on another oscillator, if
desired. Since clocks are running in Idle mode, power consumption is dependent upon the system clock
frequency and the number of peripherals left in active mode before entering Idle. Stop mode and suspend
mode consume the least power because the majority of the device is shut down with no clocks active. SFR
Definition 10.1 describes the Power Control Register (PCON) used to control the C8051F380/1/2/3/4/5/6/
7/C's Stop and Idle power management modes. Suspend mode is controlled by the SUSPEND bit in the
OSCICN register (SFR Definition 19.3).
Although the C8051F380/1/2/3/4/5/6/7/C has Idle, Stop, and suspend modes available, more control over
the device power can be achieved by enabling/disabling individual peripherals as needed. Each analog
peripheral can be disabled when not in use and placed in low power mode. Digital peripherals, such as tim-
ers or serial buses, draw little power when they are not in use. Turning off oscillators lowers power con-
sumption considerably, at the expense of reduced functionality.
10.1. Idle Mode
Setting the Idle Mode Select bit (PCON.0) causes the hardware to halt the CPU and enter Idle mode as
soon as the instruction that sets the bit completes execution. All internal registers and memory maintain
their original data. All analog and digital peripherals can remain active during idle mode.
Idle mode is terminated when an enabled interrupt is asserted or a reset occurs. The assertion of an
enabled interrupt will cause the Idle Mode Selection bit (PCON.0) to be cleared and the CPU to resume
operation. The pending interrupt will be serviced and the next instruction to be executed after the return
from interrupt (RETI) will be the instruction immediately following the one that set the Idle Mode Select bit.
If Idle mode is terminated by an internal or external reset, the CIP-51 performs a normal reset sequence
and begins program execution at address 0x0000.
Note: If the instruction following the write of the IDLE bit is a single-byte instruction and an interrupt occurs
during the execution phase of the instruction that sets the IDLE bit, the CPU may not wake from Idle mode
when a future interrupt occurs. Therefore, instructions that set the IDLE bit should be followed by an
instruction that has two or more opcode bytes, for example:
// in ‘C’:
PCON |= 0x01;
PCON = PCON;
; in assembly:
ORL PCON, #01h
MOV PCON, PCON
// set IDLE bit
// ... followed by a 3-cycle dummy instruction
; set IDLE bit
; ... followed by a 3-cycle dummy instruction
If enabled, the Watchdog Timer (WDT) will eventually cause an internal watchdog reset and thereby termi-
nate the Idle mode. This feature protects the system from an unintended permanent shutdown in the event
of an inadvertent write to the PCON register. If this behavior is not desired, the WDT may be disabled by
software prior to entering the Idle mode if the WDT was initially configured to allow this operation. This pro-
vides the opportunity for additional power savings, allowing the system to remain in the Idle mode indefi-
76
Rev. 1.4
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